Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Gate sizing in MOS digital circuits with linear programming
EURO-DAC '90 Proceedings of the conference on European design automation
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
A New Statistical Optimization Algorithm for Gate Sizing
ICCD '04 Proceedings of the IEEE International Conference on Computer Design
A New Method for Design of Robust Digital Circuits
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
The impact of device parameter variations on the frequency and performance of VLSI chips
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Synergistic physical synthesis for manufacturability and variability in 45nm designs and beyond
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
| Hi-index | 0.02 |
In this paper we have applied statistical sizing in an industrial setting. Efficient implementation of the statistical sizing algorithm is achieved by utilizing a dedicated interior-point solution method. The new solution method is capable of solving a robust linear program, that is mapped onto a second-order conic program, an order of magnitude faster than the previously explored formulation. Our sizing algorithm is unique in that it represents variability in circuit delay analytically by formulating a robust linear program. The algorithm allows efficient and superior area minimization under statistically formulated timing yield constraints. In this paper, we also report the first use of statistical gate sizing in an industrial microprocessor design flow as a post-synthesis optimization step. Statistical delay models were generated for a 90nm CMOS standard cell library used in the design of an industrial low-power 32bit x86 microprocessor and practical issues related to iterative convergence were explored. When compared to the deterministic sizing, the area savings are 26% for the microprocessor module. The runtime of the algorithm is very low compared to existing statistical sizing methods, achieving an almost 15X speed-up, and scales as O(N1.5), where N is the circuit size.