Using randomization to cope with circuit uncertainty

Authors:
Hamid Safizadeh;Mohammad Tahghighi;Ehsan K. Ardestani;Gholamhossein Tavasoli;Kia Bazargan
Affiliations:
Institute for Research in Fundamental Sciences, Tehran, Iran;Isfahan University of Technology, Isfahan, Iran;University of California Santa Cruz, Santa Cruz, CA;Isfahan University of Technology, Isfahan, Iran;Isfahan University of Technology, Isfahan, Iran and University of Minnesota, Minneapolis, MN
Venue:
Proceedings of the Conference on Design, Automation and Test in Europe
Year:
2009

Citing 9
Cited 0

Molecular electronics: devices, systems and tools for gigagate, gigabit chips

Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Death, taxes and failing chips

Proceedings of the 40th annual Design Automation Conference
Design for Variability in DSM Technologies

ISQED '00 Proceedings of the 1st International Symposium on Quality of Electronic Design
First-order incremental block-based statistical timing analysis

Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal

Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Design and Analysis of Randomized Algorithms: Introduction to Design Paradigms (Texts in Theoretical Computer Science. An EATCS Series)

Design and Analysis of Randomized Algorithms: Introduction to Design Paradigms (Texts in Theoretical Computer Science. An EATCS Series)
Defects, Yield, and Design in Sublithographic Nano-electronics

DFT '05 Proceedings of the 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
Defining statistical sensitivity for timing optimization of logic circuits with large-scale process and environmental variations

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design

Quantified Score

Hi-index	0.00

Visualization

Abstract

Future computing systems will feature many cores that run fast, but might show more faults compared to existing CMOS technologies. New software methodologies must be adopted to utilize communication bandwidth and the computational power of few slow, reliable cores that could be employed in such systems to verify the results of the fast, faulty cores. Employing the traditional Triple Module Redundancy (TMR) at core instruction level would not be as effective due to its blind replication of computations. We propose two software development methods that utilize what we call Smart TMR (STMR) and fingerprinting to statistically monitor the results of computations and selectively replicate computations that exhibit faults. Experimental results show significant speedup and reliability improvement over traditional TMR approaches.