Gate sizing using a statistical delay model
DATE '00 Proceedings of the conference on Design, automation and test in Europe
Fast statistical timing analysis by probabilistic event propagation
Proceedings of the 38th annual Design Automation Conference
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
A methodology to improve timing yield in the presence of process variations
Proceedings of the 41st annual Design Automation Conference
Block-based Static Timing Analysis with Uncertainty
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
A timing dependent power estimation framework considering coupling
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A timing-dependent power estimation framework considering coupling
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Fitting standard cell performance to generalized Lambda distributions
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
On the computation of criticality in statistical timing analysis
Proceedings of the International Conference on Computer-Aided Design
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hi-index | 0.00 |
The increased dominance of intra-die process variations has motivated the field of Statistical Static Timing Analysis (SSTA) and has raised the need for SSTA-based circuit optimization. In this paper, we propose a new sensitivity based, statistical gate sizing method. Since brute-force computation of the change in circuit delay distribution to gate size change is computationally expensive, we propose an efficient and exact pruning algorithm. The pruning algorithm is based on a novel theory of perturbation bounds which are shown to decrease as they propagate through the circuit. This allows pruning of gate sensitivities without complete propagation of their perturbations. We apply our proposed optimization algorithm to ISCAS benchmark circuits and demonstrate the accuracy and efficiency of the proposed method. Our results show an improvement of up to 10.5% in the 99-percentile circuit delay for the same circuit area, using the proposed statistical optimizer and a run time improvement of up to 56x compared to the brute-force approach.