IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Design and reliability challenges in nanometer technologies
Proceedings of the 41st annual Design Automation Conference
Novel sizing algorithm for yield improvement under process variation in nanometer technology
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Based Optimization using Gate Sizing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
Statistical design and optimization of SRAM cell for yield enhancement
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Variability in sub-100nm SRAM designs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Statistical analysis of SRAM cell stability
Proceedings of the 43rd annual Design Automation Conference
A methodology for statistical estimation of read access yield in SRAMs
Proceedings of the 45th annual Design Automation Conference
Comparative Analysis of Timing Yield Improvement under Process Variations of Flip-Flops Circuits
ISVLSI '09 Proceedings of the 2009 IEEE Computer Society Annual Symposium on VLSI
Statistical design of the 6T SRAM bit cell
IEEE Transactions on Circuits and Systems Part I: Regular Papers
Reducing SRAM power using fine-grained wordline pulsewidth control
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Circuits and Systems Part I: Regular Papers
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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SRAM has become the dominant block in modern ICs and constitutes more than 50% of the die area. The increase of process variations with continued CMOS technology scaling is considered one of the major challenges for SRAM designers. This process variations increase causes the SRAM cells to functionally fail and reduces the chip functional yield considering the static noise margin stability failures (i.e., cell flips when accessed), write failures (i.e., cell is not written within the write window), and read access failures (i.e., incorrect read operation). In this paper, novel negative capacitance circuits are developed, for the first time, to statistically improve the SRAM read access yield under process variations by reducing the bitlines parasitic capacitance. Post layout simulation results, referring to an industrial hardware-calibrated TSMC 65-nm CMOS technology, show that the adoption of the negative capacitance circuit to a 512 SRAM cells column is capable of improving the read access yield from 61.9% to 100%.