PATMOS'10 Proceedings of the 20th international conference on Integrated circuit and system design: power and timing modeling, optimization and simulation
Statistical SRAM read access yield improvement using negative capacitance circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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In synchronous systems, any violation of the timing constraints of the flip-flops can cause the overall system to malfunction. Moreover, the process variations create a large variability in the flip-flop delay in scaled technologies impacting the timing yield. Overtime, many gate sizing algorithms have been introduced to improve the timing yield. This paper presents an analysis of timing yield improvement of four commonly used flip-flops under process variations. These flip-flops are designed using STMicroelectronics 65-nm CMOS technology. The analyzed flip-flops are compared for power and power-delay product (PDP) overheads to achieve this timing yield improvement. The analysis shows that the sense amplifier based flip flop (SA-FF) has a power overhead and PDP overhead of 1.7X and 2.8X, respectively, much higher than that of the transmission-gate master-slave flip flop(TG-MSFF) . The TG-MSFF exhibits the lowest relative power and PDP overheads of 30.87% and 9% ,respectively.