Statistical Timing Based Optimization using Gate Sizing
Proceedings of the conference on Design, Automation and Test in Europe - Volume 1
High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Non-linear statistical static timing analysis for non-Gaussian variation sources
Proceedings of the 44th annual Design Automation Conference
Static Timing Analysis for Nanometer Designs: A Practical Approach
Static Timing Analysis for Nanometer Designs: A Practical Approach
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP
IEEE Design & Test
First-Order Incremental Block-Based Statistical Timing Analysis
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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It is well known that random fluctuations in integrated circuit manufacturing introduce variations in circuit performance. While a lot of effort has been spent on circuit variability, fitting performance parameter distributions has not been extensively examined. Our work analyzes whether the Generalized Lambda Distribution suits approximating circuit performance characteristics. We focus on statistical standard cell characterization as an important step towards statistical gate-level and system-level analyses. Our results show that the Generalized Lambda Distribution is not applicable to raw leakage power data. However, timing data and dynamic power consumption may be approximated well. The high characterization effort has to be overcome to achieve industrial application.