Lagrangian relaxation for gate implementation selection
Proceedings of the 2011 international symposium on Physical design
Fitting standard cell performance to generalized Lambda distributions
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Power efficient partial product compression
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A fast approach for static timing analysis covering all PVT corners
Proceedings of the 48th Design Automation Conference
Clock tree resynthesis for multi-corner multi-mode timing closure
Proceedings of the 2014 on International symposium on physical design
TAU 2014 contest on removing common path pessimism during timing analysis
Proceedings of the 2014 on International symposium on physical design
Timing characterization and constraining tool
Microelectronics Journal
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The book covers topics such as cell timing and power modeling; interconnect modeling and analysis, delay calculation, crosstalk, noise and the chip timing verification using static timing analysis. For each of these topics, the book provides a theoretical background as well as detailed examples to elaborate the concepts. The static timing analysis topics covered start from verification of simple blocks useful for a beginner to this field. The topics then extend to complex nanometer designs with in-depth treatment of concepts such as modeling of on-chip variation, clock gating, half-cycle paths, as well as timing of source-synchronous interfaces such as DDR. The impact of crosstalk on timing and noise is covered as is the usage of hierarchical design methodology. This book addresses CMOS logic gates, cell library, timing arcs, waveform slew, cell capacitance, timing modeling, interconnect parasitics and coupling, pre- and post-layout interconnect modeling, delay calculation, specification of timing constraints for analysis of internal paths as well as IO interfaces. Advanced modeling and analysis concepts such as controlled current source timing and noise models for nanometer technologies, power modeling including active and leakage power, crosstalk timing and crosstalk glitch calculation, verification of half-cycle and multi-cycle paths, false paths, synchronous interfaces are also covered.