Timing-driven placement for FPGAs
FPGA '00 Proceedings of the 2000 ACM/SIGDA eighth international symposium on Field programmable gate arrays
Uncertainty-aware circuit optimization
Proceedings of the 39th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Computation and Refinement of Statistical Bounds on Circuit Delay
Proceedings of the 40th annual Design Automation Conference
First-order incremental block-based statistical timing analysis
Proceedings of the 41st annual Design Automation Conference
Statistical Timing Analysis for Intra-Die Process Variations with Spatial Correlations
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Circuit optimization using statistical static timing analysis
Proceedings of the 42nd annual Design Automation Conference
Proceedings of the 42nd annual Design Automation Conference
Variation Aware Placement for FPGAs
ISVLSI '06 Proceedings of the IEEE Computer Society Annual Symposium on Emerging VLSI Technologies and Architectures
Speed binning aware design methodology to improve profit under parameter variations
ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference
FPGA device and architecture evaluation considering process variations
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
ICCAD '05 Proceedings of the 2005 IEEE/ACM International conference on Computer-aided design
An adaptive FPGA architecture with process variation compensation and reduced leakage
Proceedings of the 43rd annual Design Automation Conference
Variation-aware routing for FPGAs
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Analysis and modeling of CD variation for statistical static timing
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Statistical timing analysis under spatial correlations
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Evaluation of FPGA routing architectures under process variation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Yield loss due to timing failures results in diminished returns for field-programmable gate arrays (FPGAs), and is aggravated under increased process variations in scaled technologies. The uncertainty in the critical delay of a circuit under process variations exists because the delay of each logic element in the circuit is no longer deterministic. Traditionally, FPGAs have been designed to manage process variations through speed binning, which works well for inter-die variations, but not for intra-die variations resulting in reduced timing yield for FPGAs. FPGAs present a unique challenge because of their programmability and unknown end user application. In this paper, a novel architecture and computer-aided design co-design technique is proposed to improve the timing yield. Experimental results indicate that the use of proposed design technique can achieve timing yield improvement of up to 68%.