Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Mismatch Modeling and Simulation—A Comprehensive Approach
Analog Integrated Circuits and Signal Processing
Parameter variations and impact on circuits and microarchitecture
Proceedings of the 40th annual Design Automation Conference
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis
Proceedings of the 2007 ACM/SIGDA 15th international symposium on Field programmable gate arrays
Suppression of Intrinsic Delay Variation in FPGAs using Multiple Configurations
ACM Transactions on Reconfigurable Technology and Systems (TRETS) - Special edition on the 15th international symposium on FPGAs
Parametric Yield Modeling and Simulations of FPGA Circuits Considering Within-Die Delay Variations
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
TuneFPGA: post-silicon tuning of dual-Vdd FPGAs
Proceedings of the 45th annual Design Automation Conference
FPGA Architecture: Survey and Challenges
Foundations and Trends in Electronic Design Automation
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the Conference on Design, Automation and Test in Europe
Evaluation of FPGA routing architectures under process variation
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Limit study of energy & delay benefits of component-specific routing
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Journal of Electronic Testing: Theory and Applications
Energy attacks and defense techniques for wireless systems
Proceedings of the sixth ACM conference on Security and privacy in wireless and mobile networks
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Process induced threshold voltage variations bring about fluctuations in circuit delay, that affect the FPGA timing yield. We propose an adaptive FPGA architecture that compensates for these fluctuations. The architecture includes an additional characterizer circuit that classifies logic and routing blocks on each die according to their performance. Based on this classification, the architecture adaptively body-biases these resources by either speeding up the slow blocks or by slowing down the leaky ones. This procedure mitigates the effect of the variations and provides a better yield. We further diminish leakage by slowing down areas of the FPGA that have a positive slack. Overall, this architecture minimizes the timing variance of within-die and die-to-die Vth variations by up to 3.45X and reduces leakage power in the non-critical areas of the FPGA by 3X with no effect on frequency.