Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
RASP: a general logic synthesis system for SRAM-based FPGAs
Proceedings of the 1996 ACM fourth international symposium on Field-programmable gate arrays
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
On gate level power optimization using dual-supply voltages
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Level conversion for dual-supply systems
Proceedings of the 2003 international symposium on Low power electronics and design
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Delay optimal low-power circuit clustering for FPGAs with dual supply voltages
Proceedings of the 2004 international symposium on Low power electronics and design
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Combining low-leakage techniques for FPGA routing design
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Fine-grain leakage optimization in SRAM based FPGAs
GLSVLSI '05 Proceedings of the 15th ACM Great Lakes symposium on VLSI
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Device and architecture co-optimization for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
LAP: a logic activity packing methodology for leakage power-tolerant FPGAs
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Evaluation of dual VDD fabrics for low power FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Dual-Vt Design of FPGAs for Subthreshold Leakage Tolerance
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Energy-efficient FPGA interconnect design
Proceedings of the conference on Design, automation and test in Europe: Designers' forum
An analytical state dependent leakage power model for FPGAs
Proceedings of the conference on Design, automation and test in Europe: Proceedings
Leakage power reduction of embedded memories on FPGAs through location assignment
Proceedings of the 43rd annual Design Automation Conference
An adaptive FPGA architecture with process variation compensation and reduced leakage
Proceedings of the 43rd annual Design Automation Conference
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
An overview of reconfigurable hardware in embedded systems
EURASIP Journal on Embedded Systems
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Architectural enhancements in Stratix-III™ and Stratix-IV™
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA
IEICE - Transactions on Information and Systems
Development of field programmable modular wireless sensor network nodes for ambient systems
Computer Communications
A low-power field-programmable gate array routing fabric
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Fully-functional FPGA prototype with fine-grain programmable body biasing
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Low power FPGA design using post-silicon device aging (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Energy proportional computing in commercial FPGAs with adaptive voltage scaling
Proceedings of the 10th FPGAworld Conference
Energy-efficient scheduling on multi-FPGA reconfigurable systems
Microprocessors & Microsystems
A FPGA prototype design emphasis on low power technique
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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Traditional FPGAs use uniform supply voltage Vdd and uniform threshold voltage Vt. We propose to use pre-defined dual-Vdd and dual-Vt fabrics to reduce FPGA power. We design FPGA circuits with dual-Vdd/dual-Vt to effectively reduce both dynamic power and leakage power, and define dual-Vdd/dual-Vt FPGA fabrics based on the profiling of benchmark circuits. We further develop CAD algorithms including power-sensitivity based voltage assignment and simulated-annealing based placement to leverage such fabrics. Compared to the conventional fabric using uniform Vdd/Vt at the same target clock frequency, our new fabric using dual Vt achieves 9% to 20% power reduction. However, the pre-defined FPGA fabric using both dual Vdd and dual Vt only achieves on average 2% extra power reduction. It is because that the pre-designed dual-Vdd layout pattern introduces non-negligible performance penalty. Therefore, programmability of supply voltage is needed to achieve significant power saving for dual-Vdd FPGAs. To our best knowledge, it is the first in-depth study on applying both dual-Vdd and dual-Vt to FPGA considering circuits, fabrics and CAD algorithms.