Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Measuring the Gap Between FPGAs and ASICs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Voltage and frequency adaptation can be used to create energy proportional systems in which energy usage adapts to the amount of work to be done in the available time. Closed-loop voltage and frequency scaling can also take into account process and temperature variations in addition to system load and this removes a significant proportion of the margins used by device manufacturers. This paper explores the capabilities of commercial FPGAs to use closed-loop adaptive voltage scaling to improve their energy and performance profiles beyond nominal. An adaptive power architecture based on a modified design flow is created with in-situ detectors and dynamic reconfiguration of clock management resources. The results of deploying AVS in FPGAs shows power and energy savings exceeding 85% compared with nominal voltage operation at the same frequency or 100% better performance at nominal energy. The in-situ detector approach compares favorably with critical path replication based on delay lines since it avoids the need of cumbersome and error-prone delay line calibration.