Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
A Flexible Power Model for FPGAs
FPL '02 Proceedings of the Reconfigurable Computing Is Going Mainstream, 12th International Conference on Field-Programmable Logic and Applications
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Active leakage power optimization for FPGAs
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Optimization of the Body Bias Voltage Set (BBVS) for Flex Power FPGA
IEICE - Transactions on Information and Systems
High speed interconnect through device optimization for subthreshold FPGA
Microelectronics Journal
Performance analysis of FPGA interconnect fabric for ultra-low power applications
Proceedings of the 2011 International Conference on Communication, Computing & Security
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A configurable architecture to limit wakeup current in dynamically-controlled power-gated FPGAs
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires
Microelectronics Journal
Fully-functional FPGA prototype with fine-grain programmable body biasing
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Power has become an increasingly important design constraint for FPGAs in nanometer technologies, and global interconnects should be the focus of FPGA power reduction as they consume more power than logic cells. We design area-efficient circuits for programmable fine-grained power-gating of individual unused interconnect switches, and reduce interconnect leakage power dramatically because the interconnect switches have an intrinsically low utilization rate for the purpose of programmability. The low leakage interconnect via power-gating reduces total power by 38.18% for the FPGA in 100nm technology. Furthermore, it enables interconnect dynamic power reduction. We design a routing channel containing abundant or duplicated routing tracks with pre-determined high and low Vdd, and develop routing algorithm using low Vdd for non-critical routing to reduce dynamic power. The track-duplicated routing channel has small leakage power and increase the FPGA power reduction to 45.00%.