Fundamentals of modern VLSI devices
Fundamentals of modern VLSI devices
Effects of inductance on the propagation delay and repeater insertion in VLSI circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Sub-threshold Design for Ultra Low-Power Systems (Series on Integrated Circuits and Systems)
Proceedings of the 2007 international symposium on Physical design
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Field Programmability of Supply Voltages for FPGA Power Reduction
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Robustness comparison of emerging devices for portable applications
Journal of Nanomaterials
Reducing expected delay and power in FPGAs using buffer insertion in single-driver wires
Microelectronics Journal
Interconnect optimization to enhance the performance of subthreshold circuits
Microelectronics Journal
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Field programmable gate array (FPGA) consumes a significant amount of static and dynamic power due to the presence of additional logic for providing more flexibility as compared to application specific integrated circuits (ASICs). The fabrication cost of ASICs is rising exponentially in deep submicron and hence it is important to investigate different techniques for reducing FPGA power consumption so that they can also be employed in place of ASICs in portable energy constrained applications. It is also important to investigate the possibility of extending the use of FPGA even to subthreshold region for ultra low power (ULP) applications. Interconnect resources of an FPGA consumes most of the chip power, area and also determines the overall circuit delay. Subthreshold circuits show orders of magnitude power saving over superthreshold circuits. Improving the performance of subthreshold circuits is a main design challenge at the circuit and device levels to spread their application area. This paper proposes to improve the performance of subthreshold FPGA in terms of delay and switching energy by optimizing and operating interconnect drivers in the near threshold operating region. The possibility of inserting repeaters and the suitability of CNT as an interconnect in the subthreshold region are also explored. The simulation of FPGA interconnect resources using the proposed technique shows 67%, 73.33% and 61.8% increase in speed and 35.72%, 39% and 35.44% reduction in switching energy for Double, Hex and Long interconnect segments, respectively, over the conventional one.