Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Robust subthreshold logic for ultra-low power operation
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special issue on low power electronics and design
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power modeling and characteristics of field programmable gate arrays
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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Fabrication cost of ASICs is increases rapidly for deep submicron technology. It is important to explore the different techniques to reduce the FPGA power consumption so that in future they can also be deploy in place of ASICs in portable energy constrained applications. Since power is an important design constrain for FPGA in nanometer technology, it is important to investigate the possibility of extending the use of FPGA to the subthreshold region for ultra low power applications. Interconnect fabric of an FPGA consumes a large amount of the chip power, area and determines the overall circuit delay. Exponential increase in resistance of interconnects driver in subthreshold region gives huge penalty in terms of speed of FPGA interconnect fabric. Improving speed is one of the subthreshold circuit design challenge. In particular, this paper investigates the performance of FPGA interconnect resource using CMOS, Carbon Nano Tube Transistors (CNFETs), FinFET and operating drivers in near threshold region. The proposed interconnect fabric in which drivers are operated in near threshold voltage shows 3.6 X, 3X and 1.25X improvement in speed over conv. CMOS, Opt-CNFET and FINFET driver based HEX interconnect resource.