MTCMOS hierarchical sizing based on mutual exclusive discharge patterns
DAC '98 Proceedings of the 35th annual Design Automation Conference
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Architecture evaluation for power-efficient FPGAs
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Methods for true power minimization
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Distributed sleep transistor network for power reduction
Proceedings of the 40th annual Design Automation Conference
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Reducing leakage energy in FPGAs using region-constrained placement
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
On optimal physical synthesis of sleep transistors
Proceedings of the 2004 international symposium on Physical design
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Device and architecture co-optimization for FPGA power reduction
Proceedings of the 42nd annual Design Automation Conference
Low-power programmable routing circuitry for FPGAs
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
Vdd programmability to reduce FPGA interconnect power
Proceedings of the 2004 IEEE/ACM International conference on Computer-aided design
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
Routing track duplication with fine-grained power-gating for FPGA interconnect power reduction
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Leakage control in FPGA routing fabric
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Evaluation of dual VDD fabrics for low power FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal module and voltage assignment for low-power
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
Optimal simultaneous module and multivoltage assignment for low power
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction
Proceedings of the 43rd annual Design Automation Conference
Optimality study of resource binding with multi-Vdds
Proceedings of the 43rd annual Design Automation Conference
An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction
Proceedings of the 2006 international symposium on Low power electronics and design
Post-placement leakage optimization for partially dynamically reconfigurable FPGAs
ISLPED '07 Proceedings of the 2007 international symposium on Low power electronics and design
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming
ACM Transactions on Design Automation of Electronic Systems (TODAES)
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A high-level clustering algorithm targeting dual Vdd FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Clock power reduction for virtex-5 FPGAs
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Architectural enhancements in Stratix-III™ and Stratix-IV™
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Leakage-aware task scheduling for partially dynamically reconfigurable FPGAs
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power programmable FPGA routing circuitry
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Low-power 3D nano/CMOS hybrid dynamically reconfigurable architecture
ACM Journal on Emerging Technologies in Computing Systems (JETC)
Bandwidth Management in Application Mapping for Dynamically Reconfigurable Architectures
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Technology mapping and clustering for FPGA architectures with dual supply voltages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only)
Proceedings of the 19th ACM/SIGDA international symposium on Field programmable gate arrays
An enhanced leakage-aware scheduler for dynamically reconfigurable FPGAs
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Circuits and architectures for field programmable gate array with configurable supply voltage
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Statistical Timing and Power Optimization of Architecture and Device for FPGAs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Adaptive Voltage Scaling in a Dynamically Reconfigurable FPGA-Based Platform
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
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Power optimization is of growing importance for FPGAs in nanometer technologies. Considering dual-Vdd technique, we show that configurable power supply is required to obtain a satisfactory performance and power tradeoff. We design FPGA circuits and logic fabrics using configurable dual-Vdd and develop the corresponding CAD flow to leverage such circuits and logic fabrics. We then carry out a highly quantitative study using area, delay and power models obtained from detailed circuit design and SPICE simulation in 100nm technology. Compared to single-Vdd FPGAs with optimized Vdd level for the same target clock frequency, configurable dual-Vdd FPGAs with full and partial supply programmability for logic blocks reduce logic power by 35.46% and 28.62% respectively and reduce total FPGA power by 14.29% and 9.04% respectively. To the best of our knowledge, it is the first in-depth study on FPGAs with configurable dual-Vdd for power reduction.