Comparing algorithm for dynamic speed-setting of a low-power CPU
MobiCom '95 Proceedings of the 1st annual international conference on Mobile computing and networking
Low-energy embedded FPGA structures
ISLPED '98 Proceedings of the 1998 international symposium on Low power electronics and design
Gate-level design exploiting dual supply voltages for power-driven applications
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Low-power design methodology and applications utilizing dual supply voltages
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Power minization in LUT-based FPGA technology mapping
Proceedings of the 2001 Asia and South Pacific Design Automation Conference
Dynamic voltage scaling and power management for portable systems
Proceedings of the 38th annual Design Automation Conference
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Power efficiency of voltage scaling in multiple clock, multiple voltage cores
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Pushing ASIC performance in a power envelope
Proceedings of the 40th annual Design Automation Conference
Power minimization algorithms for LUT-based FPGA technology mapping
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Low-power technology mapping for FPGA architectures with dual supply voltages
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
On the Interaction Between Power-Aware FPGA CAD Algorithms
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
FPGA Design Automation: A Survey
Foundations and Trends in Electronic Design Automation
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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Power efficiency is becoming an increasingly important design aspect for FPGAs. Recently it has been shown that well-known power minimization techniques in the ASICs such as creating supply voltage (Vdd) scalable islands of different granularity can be applied to FPGAs. However, the discrete routing architecture of FPGAs amplifies any constraint imposed on the placement stage. In this work, we evaluate the overheads of voltage scaling schemes in relation to FPGA architectures and design flows in terms of critical path delay, channel-width and area/delay product. We present a detailed evaluation of the impact of alternative realizations of voltage scaling schemes onto the physical design flow of FPGAs and show that as high as 47% dynamic power gain is possible with 17% area/delay product penalty and 30% power gain is possible with as low as 6% area/delay product penalty for different voltage island configurations.