FPGA routing architecture: segmentation and buffering to optimize speed and density
FPGA '99 Proceedings of the 1999 ACM/SIGDA seventh international symposium on Field programmable gate arrays
Low Energy Switch Block For FPGAs
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
Evaluation of dual VDD fabrics for low power FPGAs
Proceedings of the 2005 Asia and South Pacific Design Automation Conference
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We compare circuit and architecture choices in the global interconnect of an FPGA in order to find the minimum energy design for low voltage operation. We look at switch box topology, number of repeaters, receiver circuit topology, and dynamic voltage selection, all with the intent of minimizing energy consumption. The results show that using a pass gate switchbox topology with repeaters in the interconnect and a custom receiver lowers delay by up to 63% and energy by up to 87% from the standard FPGA circuit choices. This work also identifies the optimal VDD choices to maximize performance under energy constraints or vice versa.