Low energy FPGA interconnect design
Proceedings of the 14th ACM Great Lakes symposium on VLSI
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
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We propose a new energy efficient method of designingswitch blocks inside FPGAs using novel variations of the Dual ThresholdCMOS (DTMOS) based switches instead of the conventional NMOSpass transistor or tri-state buffer based switches. By intelligently sharingthe extra transistor needed for using DTMOS based switches, the areaoverhead is kept to a minimum. Sleep transistors are used to reducesub-threshold leakage. Using our new, novel design, we obtain a 16%improvement in the power-delay product during the active mode perswitch and a factor of 20 improvement in the stand-by mode, overconventional approaches. Extensive simulation results over benchmarkcircuits in CMOS 0.13µ are presented to illustrate the superiority of theproposed techniques. Since the proposed techniques target the switchesand multiplexers which are present in large numbers on FPGAs, theoverall improvement in the power-delay product is significant for anapplication implemented on a FPGA having the proposed features.