Bus-invert coding for low-power I/O
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Digital integrated circuits: a design perspective
Digital integrated circuits: a design perspective
Dynamic power consumption in Virtex™-II FPGA family
FPGA '02 Proceedings of the 2002 ACM/SIGDA tenth international symposium on Field-programmable gate arrays
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Low Energy Switch Block For FPGAs
VLSID '04 Proceedings of the 17th International Conference on VLSI Design
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We propose a new low energy FPGA interconnect fabric that is based on low energy switch blocks using Dynamic Threshold CMOS (DTMOS) based switches and an encoded-low swing (EL) technique. The presented case study illustrates that the encoded-low swing technique and Dual Threshold MOS based switches results in 41% energy reduction compared to the conventional technique using full swing signalling and NMOS pass transistor based switches. We also show through a theoretical analysis, that a certain timing budget can be met by the EL technique, using 11% more buffered switches, but still consuming 62% less energy than conventional techniques. Circuit simulations, taking also the transmitter and receiver complexity into account, are in line with the model results and indicate that a timing budget can be met at 30% less energy consumption. All our results are based on CMOS 0.13μ process technology and are done using a transistor level simulator.