Gate-level design exploiting dual supply voltages for power-driven applications

Power reduction by simultaneous voltage scaling and gate sizing

ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference

On gate level power optimization using dual-supply voltages

IEEE Transactions on Very Large Scale Integration (VLSI) Systems

Dual Supply Voltage Scaling in a Conventional Power-Driven Logic Synthesis Environment

PATMOS '02 Proceedings of the 12th International Workshop on Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation

Low-power technology mapping for FPGA architectures with dual supply voltages

FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays

Delay optimal low-power circuit clustering for FPGAs with dual supply voltages

Proceedings of the 2004 international symposium on Low power electronics and design

Power distribution techniques for dual VDD circuits

ASP-DAC '06 Proceedings of the 2006 Asia and South Pacific Design Automation Conference

Evaluation of dual VDD fabrics for low power FPGAs

Proceedings of the 2005 Asia and South Pacific Design Automation Conference

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

A high-level clustering algorithm targeting dual Vdd FPGAs

ACM Transactions on Design Automation of Electronic Systems (TODAES)

Low-power design techniques for scaled technologies

Integration, the VLSI Journal - Special issue: Low-power design techniques

Technology mapping and clustering for FPGA architectures with dual supply voltages

IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems