Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
FPGA power reduction using configurable dual-Vdd
Proceedings of the 41st annual Design Automation Conference
The Stratix II logic and routing architecture
Proceedings of the 2005 ACM/SIGDA 13th international symposium on Field-programmable gate arrays
A 90nm low-power FPGA for battery-powered applications
Proceedings of the 2006 ACM/SIGDA 14th international symposium on Field programmable gate arrays
A PUF design for secure FPGA-based embedded systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Low-cost sensing with ring oscillator arrays for healthier reconfigurable systems
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A routing architecture for FPGAs with Dual-VT switch box and logic clusters
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Fully-functional FPGA prototype with fine-grain programmable body biasing
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Architectural enhancements in Stratix V™
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Optimizing floating point units in hybrid FPGAs
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
A FPGA prototype design emphasis on low power technique
Proceedings of the 2014 ACM/SIGDA international symposium on Field-programmable gate arrays
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This paper describes architectural enhancements in the Stratix-III" and Stratix-IV" FPGA architectures. These architectures feature programmable power management, which allows the power and performance of logic and routing to be varied to minimize total power without any performance loss. This paper describes the technique used for programmable power management, and describes the experimental evaluation that led to the choice of regions in these architectures. The memory architecture is also explored by adding heterogeneous memory mapping to the FPGA Modeling Toolkit, and used to explore LUT based memory structures. The ALM structure provides more inputs than required for a simple 6 LUT, which can be used with simple modifications to efficiently support simple dual-ported LUT based RAM. Replacing the Stratix-II" small memory blocks with LUT RAM and changing the size of other two memories is shown to reduce overall core area across a set of benchmark designs.