Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
EPIC: ending piracy of integrated circuits
Proceedings of the conference on Design, automation and test in Europe
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Techniques for Design and Implementation of Secure Reconfigurable PUFs
ACM Transactions on Reconfigurable Technology and Systems (TRETS)
Architectural enhancements in Stratix-III™ and Stratix-IV™
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Performance and security evaluation of AES s-box-based glitch PUFs on FPGAs
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Computers and Electrical Engineering
Design and implementation of a group-based RO PUF
Proceedings of the Conference on Design, Automation and Test in Europe
An FPGA chip identification generator using configurable ring oscillators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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The concept of having an integrated circuit (IC) generate its own unique digital signature has broad application in areas such as embedded systems security, and IP/IC counter-piracy. Physically unclonable functions (PUFs) are circuits that compute a unique signature for a given IC based on the process variations inherent in the IC manufacturing process. This paper presents the first PUF design specifically targeted for field-programmable gate arrays (FPGAs). Our novel design makes use of the underlying FPGA architecture, and unlike prior published PUFs, the proposed PUF can be naturally embedded into a design's HDL, consuming very little area, and does not require the use of "hard macros" with fixed routing. Measured results on the Xilinx Virtex-5 65 nm FPGA demonstrate PUF signatures to be both unique and reliable under temperature variation.