Extended abstract: The butterfly PUF protecting IP on every FPGA

  • Authors:
  • Sandeep S. Kumar;Jorge Guajardo;Roel Maes;Geert-Jan Schrijen;Pim Tuyls

  • Affiliations:
  • Philips Research Europe, 5656 AE, Eindhoven, THE NETHERLANDS;Philips Research Europe, 5656 AE, Eindhoven, THE NETHERLANDS;K.U.Leuven, ESAT/COSIC, B-3001 Heverlee, BELGIUM;Philips Research Europe, 5656 AE, Eindhoven, THE NETHERLANDS;Philips Research Europe, 5656 AE, Eindhoven, THE NETHERLANDS

  • Venue:
  • HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
  • Year:
  • 2008

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Abstract

IP protection of hardware designs is the most important requirement for many FPGA IP vendors. To this end, various solutions have been proposed by FPGA manufacturers based on the idea of bitstream encryption. An alternative solution was advocated in [18]. Simpson and Schaumont proposed in [18] a new approach based on Physical Unclonable Functions (PUFs) for IP protection on FPGAs. PUFs are a unique class of physical systems that extract secrets from complex physical characteristics of the integrated circuits which along with the properties of unclonability provide a highly secure means of generating volatile secret keys for cryptographic operations. However, the first practical PUF on an FPGA was proposed only later in [7] based on the startup values of embedded SRAM memories which are intrinsic in some of the current FPGAs. The disadvantage of these intrinsic SRAM PUFs is that not all FPGAs support uninitialized SRAM memory. In this paper, we propose a new PUF structure called the Butterfly PUF that can be used on all types of FPGAs. We also present experimental results showing their identification and key generation capabilities.