Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Statistical timing analysis based on a timing yield model
Proceedings of the 41st annual Design Automation Conference
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Efficient Helper Data Key Extractor on FPGAs
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Soft decision helper data algorithm for SRAM PUFs
ISIT'09 Proceedings of the 2009 IEEE international conference on Symposium on Information Theory - Volume 3
RFID-Tags for anti-counterfeiting
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Physically unclonable functions: manufacturing variability as an unclonable device identifier
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Uniqueness enhancement of PUF responses based on the locations of random outputting RS latches
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Clockless physical unclonable functions
TRUST'12 Proceedings of the 5th international conference on Trust and Trustworthy Computing
Performance and security evaluation of AES s-box-based glitch PUFs on FPGAs
SPACE'12 Proceedings of the Second international conference on Security, Privacy, and Applied Cryptography Engineering
Bias-based modeling and entropy analysis of PUFs
Proceedings of the 3rd international workshop on Trustworthy embedded devices
Strong PUFs and their (physical) unpredictability: a case study with power PUFs
Proceedings of the Workshop on Embedded Systems Security
An accurate probabilistic reliability model for silicon PUFs
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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In this paper we propose a new Delay-PUF architecture that is expected to solve the current problem of Delay-PUF that it is easy to predict the relation between delay information and generated information. Our architecture exploits glitches that behave non-linearly from delay variation between gates and the characteristic of pulse propagation of each gate. We call this architecture Glitch PUF. In this paper, we present a concrete structure of Glitch PUF. We then show the evaluation results on the randomness and statistical properties of Glitch PUF. In addition, we present a simple scheme to evaluate Delay-PUFs by simulation at the design stage. We show the consistency of the evaluation results for real chips and those by simulation for Glitch PUF.