Uniqueness enhancement of PUF responses based on the locations of random outputting RS latches

Authors:
Dai Yamamoto;Kazuo Sakiyama;Mitsugu Iwamoto;Kazuo Ohta;Takao Ochiai;Masahiko Takenaka;Kouichi Itoh
Affiliations:
FUJITSU LABORATORIES LTD, Nakahara-ku, Kawasaki-shi, Kanagawa, Japan;The University of Electro-Communications, Chofugaoka, Chofu, Tokyo, Japan;The University of Electro-Communications, Chofugaoka, Chofu, Tokyo, Japan;The University of Electro-Communications, Chofugaoka, Chofu, Tokyo, Japan;FUJITSU LABORATORIES LTD, Nakahara-ku, Kawasaki-shi, Kanagawa, Japan;FUJITSU LABORATORIES LTD, Nakahara-ku, Kawasaki-shi, Kanagawa, Japan;FUJITSU LABORATORIES LTD, Nakahara-ku, Kawasaki-shi, Kanagawa, Japan
Venue:
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Year:
2011

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Abstract

Physical Unclonable Functions (PUFs) are expected to represent an important solution for secure ID generation and authentication etc. In general, PUFs are considered to be more secure the larger their output entropy. However, the entropy of conventional PUFs is lower than the output bit length, because some output bits are random numbers, which are regarded as unnecessary for ID generation and discarded. We propose a novel PUF structure based on a Butterfly PUF with multiple RS latches, which generates larger entropy by utilizing location information of the RS latches generating random numbers. More specifically, while conventional PUFs generate binary values (0/1), the proposed PUF generates ternary values (0/1/random) in order to increase entropy. We estimate the entropy of the proposed PUF. According to our experiment with 40 FPGAs, a Butterfly PUF with 128 RS latches can improve entropy from 116 bits to 192.7 bits, this being maximized when the frequency of each ternary value is equal. We also show the appropriate RS latch structure for satisfying this condition, and validate it through an FPGA experiment.