Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
An Optimized S-Box Circuit Architecture for Low Power AES Design
CHES '02 Revised Papers from the 4th International Workshop on Cryptographic Hardware and Embedded Systems
Identification and authentication of integrated circuits: Research Articles
Concurrency and Computation: Practice & Experience - Computer Security
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Modeling attacks on physical unclonable functions
Proceedings of the 17th ACM conference on Computer and communications security
The glitch PUF: a new delay-PUF architecture exploiting glitch shapes
CHES'10 Proceedings of the 12th international conference on Cryptographic hardware and embedded systems
A PUF design for secure FPGA-based embedded systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
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Physical(ly) Unclonable Functions (PUFs) are expected to represent a solution for secure ID generation, authentication, and other important security applications. Researchers have developed several kinds of PUFs and self-evaluated them to demonstrate their advantages. However, both performance and security aspects of some proposals have not been thoroughly and independently evaluated. Third-party evaluation is important to discuss whether a proposal performs according to what the developers claim, regardless of any accidental bias. In this paper, we focus on Glitch PUFs (GPUFs) that use an AES S-Box implementation as a glitch generator, as proposed by Suzuki et al. [1]. They claim that this GPUF is one of the most practically feasible and secure delay-based PUFs. However, it has not been evaluated by other researchers yet. We evaluate GPUFs implemented on FPGAs and present three novel results. First, we clarify that the total number of challenge-response pairs of GPUFs is 219, instead of 211. Second, we show that a GPUF implementation has low robustness against voltage variation. Third, we point out that the GPUF has "weak" challenges leading to responses that can be more easily predictable than others by an adversary. Our results indicate that GPUFs that use the AES S-Box as the glitch generator present almost no PUF-behavior as both reliability and uniqueness are relatively low. In conclusion, our case study on FPGAs suggests that GPUFs should not use the AES S-Box as a glitch generator due to performance and security reasons.