Testing and testable design of high-density random-access memories
Testing and testable design of high-density random-access memories
Test Routines Based on Symbolic Logical Statements
Journal of the ACM (JACM)
Hot carrier degradation and time-dependent dielectric breakdown in oxides
Proceedings of the third session on Reliability in VLSI circuits : operation, manufacturing and design: operation, manufacturing and design
Proceedings of the 38th annual Design Automation Conference
Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Fault Coverage of DC Parametric Tests for Embedded Analog Amplifiers
Proceedings of the IEEE International Test Conference on Designing, Testing, and Diagnostics - Join Them
Reliability challenges for 45nm and beyond
Proceedings of the 43rd annual Design Automation Conference
Physically Unclonable Function-Based Security and Privacy in RFID Systems
PERCOM '07 Proceedings of the Fifth IEEE International Conference on Pervasive Computing and Communications
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
A March Test for Functional Faults in Semiconductor Random Access Memories
IEEE Transactions on Computers
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Reconfigurable Physical Unclonable Functions - Enabling technology for tamper-resistant storage
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Techniques for the diagnosis of switching circuit failures
FOCS '61 Proceedings of the 2nd Annual Symposium on Switching Circuit Theory and Logical Design (SWCT 1961)
A Survey of Hardware Trojan Taxonomy and Detection
IEEE Design & Test
Introduction to Hardware Security and Trust
Introduction to Hardware Security and Trust
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor
Proceedings of the 49th Annual Design Automation Conference
IEEE Spectrum
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
Essentials of Electronic Testing for Digital, Memory and Mixed-Signal VLSI Circuits
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead
Journal of Electronic Testing: Theory and Applications
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The increasing threat of counterfeit electronic components has created specialized service of testing, detection, and avoidance of such components. However, various types of counterfeit components --- recycled, remarked, overproduced, defective, cloned, forged documentation, and tampered --- pose serious threats to supply chain. Over the past few years, standards and programs have been put in place throughout the supply chain that outline testing, documenting, and reporting procedures. However, there is little uniformity in the test results among the various entities. Currently, there are no metrics for evaluating these counterfeit detection methods. In this paper, we have developed a detailed taxonomy of defects present in counterfeit components. Based on this taxonomy, a comprehensive framework has been developed to find an optimum set of detection methods considering test time, test cost, and application risks. We have also performed an assessment of all the detection methods based on the newly introduced metrics --- counterfeit defect coverage, under-covered defects, and not-covered defects.