Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Modeling attacks on physical unclonable functions
Proceedings of the 17th ACM conference on Computer and communications security
RECONFIG '10 Proceedings of the 2010 International Conference on Reconfigurable Computing and FPGAs
An Easy-to-Design PUF Based on a Single Oscillator: The Loop PUF
DSD '12 Proceedings of the 2012 15th Euromicro Conference on Digital System Design
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This paper presents a comparative study of delay Physically Unclonable Functions (PUFs) designed in CMOS-65nm technology platforms: ASIC and FPGA (Xilinx Virtex-5). The performances are analyzed for two types of silicon PUFs, namely the arbiter and the loop PUFs. For this purpose, a PUF has been specifically designed, the "mixed PUF", to allow a fair comparison between the two structures. The principle of the mixed PUF design consists on the use of the same delay chains for both PUFs. The analysis is based on PUF responses obtained at different operating conditions for 18 ASICs. Each one embeds 49 PUF instances. The comparison analysis reveals that overall the arbiter PUF structure has the worst performance when compared to the loop PUF, on both platforms.