Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA
Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
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This paper presents an easy to design Physically Unclonable Function (PUF). The proposed PUF implementation is a loop composed of $N$ identical and controllable delay chains which are serially assembled in a loop to create a single ring oscillator. The frequency discrepancies resulting from the oscillator driven by complementary combinations of the delay chains allows to characterize one device. The presented PUF, nicknamed the Loop PUF (LPUF), returns a frequency comparison of loops made of $N$ delay chains ($N\geq2$). The comparisons are done sequentially on the same structure. Unlike others PUFs based on delays, there is no specific routing constraints. Hence the LPUF is particularly flexible and easy to design. The basic use of the Loop PUF is to generate intrinsic device keys for cryptographic algorithms. It can also be used to generate challenge response pairs for simple authentication. Experiments have been carried out on CYCLONE II FPGAs to assess the performance of the LPUF, such as randomness, uniqueness and steadiness. They clearly show both the easiness of design and the quality level of the LPUF. The measurement time \emph{vs} steadiness, as well as resistance against side-channel and modeling attacks are discussed.