International Journal of Reconfigurable Computing - Special issue on Selected Papers from the International Conference on Reconfigurable Computing and FPGAs (ReConFig'10)
Evaluation of delay PUFs on CMOS 65 nm technology: ASIC vs FPGA
Proceedings of the 2nd International Workshop on Hardware and Architectural Support for Security and Privacy
A write-time based memristive PUF for hardware security applications
Proceedings of the International Conference on Computer-Aided Design
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead
Journal of Electronic Testing: Theory and Applications
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The quantitative performance indicators of Physical Unclonable Functions (PUFs)\Randomness, Steadiness, Correctness, Diffuseness and Uniqueness\are strictly defined and applied to the evaluation of 45 arbiter PUFs on Virtex-5 FPGAs. The indicators effectively reflect the characteristics of PUFs ranging from 0 to 1 with 1 being the highest performance. The indicators enable the easy measurement and intuitive understanding of PUF performances. The experimental results shows that the arbiter PUFs have excellent overall intra-device performances though a slight bit bias is indicated. The inter-device performance is moderate and will suffice for the practical use of PUFs for device authentication and so on. Additionally, the reliability of the obtained PUF performances is statistically discussed in terms of the Confidence Interval and the number of devices. This paper presents in detail the definitions of the performance indicators and the quantitative and statistical evaluation results of the arbiter PUFs.