Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
LFSR-based Hashing and Authentication
CRYPTO '94 Proceedings of the 14th Annual International Cryptology Conference on Advances in Cryptology
Secure Configuration of Field Programmable Gate Arrays
FPL '01 Proceedings of the 11th International Conference on Field-Programmable Logic and Applications
Design principles for tamper-resistant smartcard processors
WOST'99 Proceedings of the USENIX Workshop on Smartcard Technology on USENIX Workshop on Smartcard Technology
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
From the bitstream to the netlist
Proceedings of the 16th international ACM/SIGDA symposium on Field programmable gate arrays
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Efficient Helper Data Key Extractor on FPGAs
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
FPGA-based Radar Signal Processing for Automotive Driver Assistance System
RSP '09 Proceedings of the 2009 IEEE/IFIP International Symposium on Rapid System Prototyping
Extracting secret keys from integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Hardware Trojan side-channels based on physical unclonable functions
WISTP'11 Proceedings of the 5th IFIP WG 11.2 international conference on Information security theory and practice: security and privacy of mobile devices in wireless communication
Side-channel analysis of PUFs and fuzzy extractors
TRUST'11 Proceedings of the 4th international conference on Trust and trustworthy computing
Semi-invasive EM attack on FPGA RO PUFs and countermeasures
WESS '11 Proceedings of the Workshop on Embedded Systems Security
Design and implementation of a group-based RO PUF
Proceedings of the Conference on Design, Automation and Test in Europe
An FPGA chip identification generator using configurable ring oscillators
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Physical Unclonable Functions (PUFs) based on Ring Oscillators (ROs) are a promising primitive for FPGA security. However, the quality of their implementation depends on several design parameters. In this paper, we show that ring oscillator frequencies strongly depend on surrounding logic. Based on these findings, we propose a strategy for improving the quality of RO PUF designs by placing and comparing ROs in a chain-like structure. We also show that an increased RO runtime and RO disabling has a clear positive effect on the quality of a RO PUF. We implemented a RO PUF key generation system on an FPGA using our design strategy. Our results clearly indicate that our proposed design strategy can significantly improve the quality of a RO PUF implementation.