An FPGA chip identification generator using configurable ring oscillators

Authors:
Haile Yu;Philip H. W. Leong;Qiang Xu
Affiliations:
Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong;School of Electrical and Information Engineering, The University of Sydney, Sydney, New South Wales, Australia;Department of Computer Science and Engineering, The Chinese University of Hong Kong, Shatin, Hong Kong
Venue:
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Year:
2012

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Abstract

Physically unclonable functions (PUF) are commonly used in applications such as hardware security and intellectual property protection. Various PUF implementation techniques have been proposed to translate chip-specific variations into a unique binary string. It is difficult to maintain repeatability of chip ID generation, especially over a wide range of operating conditions. To address this problem, we propose utilizing configurable ring oscillators and an orthogonal re-initialization scheme to improve repeatability. An implementation on a Xilinx Spartan-3e field-programmable gate array was tested on nine different chips. Experimental results show that the bit flip rate is reduced from 1.5% to approximately 0 at a fixed supply voltage and room temperature. Over a 20 °C-80 °C temperature range and 25% variation in supply voltage, the bit flip rate is reduced from 1.56% to 3.125 × 10-7.