Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Controlled Physical Random Functions
ACSAC '02 Proceedings of the 18th Annual Computer Security Applications Conference
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Towards Robust Low Cost Authentication for Pervasive Devices
PERCOM '08 Proceedings of the 2008 Sixth Annual IEEE International Conference on Pervasive Computing and Communications
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
IEEE Transactions on Computers
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Memory Leakage-Resilient Encryption Based on Physically Unclonable Functions
ASIACRYPT '09 Proceedings of the 15th International Conference on the Theory and Application of Cryptology and Information Security: Advances in Cryptology
Low-power sub-threshold design of secure physical unclonable functions
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Modeling attacks on physical unclonable functions
Proceedings of the 17th ACM conference on Computer and communications security
Hardware intrinsic security from D flip-flops
Proceedings of the fifth ACM workshop on Scalable trusted computing
Extracting secret keys from integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Short paper: lightweight remote attestation using physical functions
Proceedings of the fourth ACM conference on Wireless network security
A Formalization of the Security Features of Physical Functions
SP '11 Proceedings of the 2011 IEEE Symposium on Security and Privacy
Logically reconfigurable PUFs: memory-based secure key storage
Proceedings of the sixth ACM workshop on Scalable trusted computing
Information-theoretic security analysis of physical uncloneable functions
FC'05 Proceedings of the 9th international conference on Financial Cryptography and Data Security
RFID-Tags for anti-counterfeiting
CT-RSA'06 Proceedings of the 2006 The Cryptographers' Track at the RSA conference on Topics in Cryptology
Robust key extraction from physical uncloneable functions
ACNS'05 Proceedings of the Third international conference on Applied Cryptography and Network Security
The context-tree weighting method: basic properties
IEEE Transactions on Information Theory
Bias-based modeling and entropy analysis of PUFs
Proceedings of the 3rd international workshop on Trustworthy embedded devices
Proceedings of the 3rd international workshop on Trustworthy embedded devices
Strong PUFs and their (physical) unpredictability: a case study with power PUFs
Proceedings of the Workshop on Embedded Systems Security
An accurate probabilistic reliability model for silicon PUFs
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
On the effectiveness of the remanence decay side-channel to clone memory-based PUFs
CHES'13 Proceedings of the 15th international conference on Cryptographic Hardware and Embedded Systems
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Physically Unclonable Functions (PUFs) are an emerging technology and have been proposed as central building blocks in a variety of cryptographic protocols and security architectures. However, the security features of PUFs are still under investigation: Evaluation results in the literature are difficult to compare due to varying test conditions, different analysis methods and the fact that representative data sets are publicly unavailable. In this paper, we present the first large-scale security analysis of ASIC implementations of the five most popular intrinsic electronic PUF types, including arbiter, ring oscillator, SRAM, flip-flop and latch PUFs. Our analysis is based on PUF data obtained at different operating conditions from 96 ASICs housing multiple PUF instances, which have been manufactured in TSMC 65 nm CMOS technology. In this context, we present an evaluation methodology and quantify the robustness and unpredictability properties of PUFs. Since all PUFs have been implemented in the same ASIC and analyzed with the same evaluation methodology, our results allow for the first time a fair comparison of their properties.