A training algorithm for optimal margin classifiers
COLT '92 Proceedings of the fifth annual workshop on Computational learning theory
Silicon physical random functions
Proceedings of the 9th ACM conference on Computer and communications security
Energy optimality and variability in subthreshold design
Proceedings of the 2006 international symposium on Low power electronics and design
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Power Analysis Attacks: Revealing the Secrets of Smart Cards (Advances in Information Security)
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Remote Password Extraction from RFID Tags
IEEE Transactions on Computers
A Survey of Lightweight-Cryptography Implementations
IEEE Design & Test
Power Analysis Attacks and Countermeasures
IEEE Design & Test
Pacemakers and Implantable Cardiac Defibrillators: Software Radio Attacks and Zero-Power Defenses
SP '08 Proceedings of the 2008 IEEE Symposium on Security and Privacy
FPGA Intrinsic PUFs and Their Use for IP Protection
CHES '07 Proceedings of the 9th international workshop on Cryptographic Hardware and Embedded Systems
Reverse-engineering a cryptographic RFID tag
SS'08 Proceedings of the 17th conference on Security symposium
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
IEEE Transactions on Computers
Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
Low-Overhead Implementation of a Soft Decision Helper Data Algorithm for SRAM PUFs
CHES '09 Proceedings of the 11th International Workshop on Cryptographic Hardware and Embedded Systems
Analysis and mitigation of process variation impacts on Power-Attack Tolerance
Proceedings of the 46th Annual Design Automation Conference
Circuit-level techniques for reliable Physically Uncloneable Functions
HST '09 Proceedings of the 2009 IEEE International Workshop on Hardware-Oriented Security and Trust
Vulnerabilities in first-generation RFID-enabled credit cards
FC'07/USEC'07 Proceedings of the 11th International Conference on Financial cryptography and 1st International conference on Usable Security
Extracting secret keys from integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Authenticating pervasive devices with human protocols
CRYPTO'05 Proceedings of the 25th annual international conference on Advances in Cryptology
Physically unclonable functions: manufacturing variability as an unclonable device identifier
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Recyclable PUFs: logically reconfigurable PUFs
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Converse PUF-Based authentication
TRUST'12 Proceedings of the 5th international conference on Trust and Trustworthy Computing
CHES'12 Proceedings of the 14th international conference on Cryptographic Hardware and Embedded Systems
PHAP: Password based Hardware Authentication using PUFs
MICROW '12 Proceedings of the 2012 45th Annual IEEE/ACM International Symposium on Microarchitecture Workshops
| Hi-index | 0.00 |
The unique and unpredictable nature of silicon enables the use of physical unclonable functions (PUFs) for chip identification and authentication. Since the function of PUFs depends on minute uncontrollable process variations, a low supply voltage can benefit PUFs by providing high sensitivity to variations and low power consumption as well. Motivated by this, we explore the feasibility of sub-threshold arbiter PUFs in 45nm CMOS technology. By modeling process variations and interconnect imbalance effects at the post-layout design level, we optimize the PUF supply voltage for the minimum power-delay product and investigate the trade-offs on PUF uniqueness and reliability. Moreover, we demonstrate that such a design optimization does not compromise the security of PUFs regarding modeling attacks and side-channel analysis attacks. Our final 64-stage sub-threshold PUF design only needs 418 gates and consumes 0.047 pJ energy per cycle, which is very promising for low-power wireless sensing and security applications.