Low Cost Attacks on Tamper Resistant Devices
Proceedings of the 5th International Workshop on Security Protocols
Managing power and performance for System-on-Chip designs using Voltage Islands
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Modeling of PMOS NBTI Effect Considering Temperature Variation
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
Understanding voltage variations in chip multiprocessors using a distributed power-delivery network
Proceedings of the conference on Design, automation and test in Europe
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Extended abstract: The butterfly PUF protecting IP on every FPGA
HST '08 Proceedings of the 2008 IEEE International Workshop on Hardware-Oriented Security and Trust
Power-Up SRAM State as an Identifying Fingerprint and Source of True Random Numbers
IEEE Transactions on Computers
Extracting secret keys from integrated circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Read-proof hardware from protective coatings
CHES'06 Proceedings of the 8th international conference on Cryptographic Hardware and Embedded Systems
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
SP '12 Proceedings of the 2012 IEEE Symposium on Security and Privacy
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Physical Unclonable Functions (PUFs) have emerged as an attractive primitive to address diverse hardware security issues in Integrated Circuits (ICs). A majority of existing PUFs rely on a dedicated circuit structure for generating chip-specific signatures, which often imposes concerns due to area/power overhead and extra design efforts. Furthermore, existing PUF-based signature generation cannot be employed to authenticate chips already in the market. In this paper, we propose RESP, a novel PUF structure realized in embedded SRAM array, a prevalent component in processors and system-on-chips (SOCs), with virtually no design modification. RESP leverages on voltage-depend memory access failures (during write) to produce large volume of high-quality challenge-response pairs. Since many modern ICs integrate SRAM array of varying size with isolated power grid, RESP can be easily retrofitted into these chips. Circuit-level simulation of 1000 chips using realistic process variation model shows high uniqueness of 49.2% average inter-die Hamming distance and good reproducibility of 2.88% intra-die Hamming distance under temperature