NBTI tolerant microarchitecture design in the presence of process variation
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI modeling in the framework of temperature variation
Proceedings of the Conference on Design, Automation and Test in Europe
A linear programming approach for minimum NBTI vector selection
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
MECCA: a robust low-overhead PUF using embedded memory array
CHES'11 Proceedings of the 13th international conference on Cryptographic hardware and embedded systems
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor
Proceedings of the 49th Annual Design Automation Conference
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
RESP: a robust physical unclonable function retrofitted into embedded SRAM array
Proceedings of the 50th Annual Design Automation Conference
| Hi-index | 0.00 |
Negative bias temperature instability (NBTI) has come to the forefront of critical reliability phenomena in advanced CMOS technology. In this paper, we propose a fast and accurate PMOS NBTI model, in which the temperature variation and the ratio of active to standby time are considered in both stress and relaxation phases. A PMOS Vth degradation model and a digital circuits' temporal performance degradation estimation method are developed based on our PMOS NBTI model. The simulation results show that: 1) our dynamic NBTI model without temperature variation is as accurate as previous models, the error is less than 2.3%; 2) the analysis error of PMOSVth degradation may reach up to 52.6% without considering temperature variation; 3) for ISCAS85 benchmark circuits, the error of worst case performance degradation analysis is about on average 52.0%; 4) the ratio of active to standby time has a considerable impact during the performance degradation analysis.