A novel gate-level NBTI delay degradation model with stacking effect

Authors:
Hong Luo;Yu Wang;Ku He;Rong Luo;Huazhong Yang;Yuan Xie
Affiliations:
Circuits and Systems Division, Dept. of EE, Tsinghua Univ., Beijing, P. R. China;Circuits and Systems Division, Dept. of EE, Tsinghua Univ., Beijing, P. R. China;Circuits and Systems Division, Dept. of EE, Tsinghua Univ., Beijing, P. R. China;Circuits and Systems Division, Dept. of EE, Tsinghua Univ., Beijing, P. R. China;Circuits and Systems Division, Dept. of EE, Tsinghua Univ., Beijing, P. R. China;CSE Department, Pennsylvania State University, University Park, PA
Venue:
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Year:
2007

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Abstract

In this paper, we propose a gate-level NBTI delay degradation model, where the stress voltage variability due to PMOS transistors' stacking effect is considered for the first time. Experimental results show that our gate-level NBTI delay degradation model results in a tighten upper bound for circuit performance analysis. The traditional circuit degradation analysis leads to on average 59.3% overestimation. The pin reordering technique can mitigate on average 6.4% performance degradation in our benchmark circuits.