High-performance CMOS variability in the 65-nm regime and beyond
IBM Journal of Research and Development - Advanced silicon technology
Combating NBTI Degradation via Gate Sizing
ISQED '07 Proceedings of the 8th International Symposium on Quality Electronic Design
NBTI-aware synthesis of digital circuits
Proceedings of the 44th annual Design Automation Conference
NBTI resilient circuits using adaptive body biasing
Proceedings of the 18th ACM Great Lakes symposium on VLSI
Facelift: Hiding and slowing down aging in multicores
Proceedings of the 41st annual IEEE/ACM International Symposium on Microarchitecture
NBTI-aware power gating for concurrent leakage and aging optimization
Proceedings of the 14th ACM/IEEE international symposium on Low power electronics and design
The impact of NBTI effect on combinational circuit: modeling, simulation, and analysis
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
NBTI-aware DVFS: a new approach to saving energy and increasing processor lifetime
Proceedings of the 16th ACM/IEEE international symposium on Low power electronics and design
Joint logic restructuring and pin reordering against NBTI-induced performance degradation
Proceedings of the Conference on Design, Automation and Test in Europe
Minimization of NBTI performance degradation using internal node control
Proceedings of the Conference on Design, Automation and Test in Europe
A linear programming approach for minimum NBTI vector selection
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
A novel gate-level NBTI delay degradation model with stacking effect
PATMOS'07 Proceedings of the 17th international conference on Integrated Circuit and System Design: power and timing modeling, optimization and simulation
Instruction-set extension under process variation and aging effects
Proceedings of the Conference on Design, Automation and Test in Europe
Incorporating the impacts of workload-dependent runtime variations into timing analysis
Proceedings of the Conference on Design, Automation and Test in Europe
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As CMOS feature size scales to the nanometer regime, transistor aging mostly due to Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI), has emerged as a major reliability concern. Threshold voltage shift causes the circuit to fail, once the post-aging delay exceeds the timing constraint. In this paper, we investigate the stacking effect of transistors on aging and propose a novel input/transistor reordering approach to alleviate the effect of NBTI and HCI during the active mode operation of the circuit. According to the results, the circuit failing due to aging effect is postponed by increasing the operational lifetime for ISCAS benchmarks by 23.6%, in average, while it has a negligible effect on delay, area, and power compared to the original cell input ordering.