Security Engineering: A Guide to Building Dependable Distributed Systems
Security Engineering: A Guide to Building Dependable Distributed Systems
Logic Synthesis and Verification Algorithms
Logic Synthesis and Verification Algorithms
Intellectual Property Metering
IHW '01 Proceedings of the 4th International Workshop on Information Hiding
Practical Cryptography
Proceedings of the 44th annual Design Automation Conference
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Remote activation of ICs for piracy prevention and digital right management
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
IEEE Spectrum
Plans for Next-Gen Chips Imperiled
IEEE Spectrum
Protecting bus-based hardware IP by secret sharing
Proceedings of the 45th annual Design Automation Conference
Active control and digital rights management of integrated circuit IP cores
CASES '08 Proceedings of the 2008 international conference on Compilers, architectures and synthesis for embedded systems
Hardware protection and authentication through netlist level obfuscation
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Detecting/preventing information leakage on the memory bus due to malicious hardware
Proceedings of the Conference on Design, Automation and Test in Europe
A PUF design for secure FPGA-based embedded systems
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Implementation and testing of high-speed CMOS true random number generators based on chaotic systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Integrated circuits metering for piracy protection and digital rights management: an overview
Proceedings of the 21st edition of the great lakes symposium on Great lakes symposium on VLSI
Securing netlist-level FPGA design through exploiting process variation and degradation
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
STEP: a unified design methodology for secure test and IP core protection
Proceedings of the great lakes symposium on VLSI
Security analysis of logic obfuscation
Proceedings of the 49th Annual Design Automation Conference
Identification of recovered ICs using fingerprints from a light-weight on-chip sensor
Proceedings of the 49th Annual Design Automation Conference
Is split manufacturing secure?
Proceedings of the Conference on Design, Automation and Test in Europe
CoARX: a coprocessor for ARX-based cryptographic algorithms
Proceedings of the 50th Annual Design Automation Conference
CLIP: circuit level IC protection through direct injection of process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Logic encryption: a fault analysis perspective
DATE '12 Proceedings of the Conference on Design, Automation and Test in Europe
SEC'13 Proceedings of the 22nd USENIX conference on Security
Proceedings of the 2014 on International symposium on physical design
Counterfeit Integrated Circuits: Detection, Avoidance, and the Challenges Ahead
Journal of Electronic Testing: Theory and Applications
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As semiconductor manufacturing requires greater capital investments, the use of contract foundries has grown dramatically, increasing exposure to mask theft and unauthorized excess production. While only recently studied, IC piracy has now become a major challenge for the electronics and defense industries [6]. We propose a novel comprehensive technique to end piracy of integrated circuits (EPIC). It requires that every chip be activated with an external key, which can only be generated by the holder of IP rights, and cannot be duplicated. EPIC is based on (i) automatically-generated chip IDs, (ii) a novel combinational locking algorithm, and (iii) innovative use of public-key cryptography. Our evaluation suggests that the overhead of EPIC on circuit delay and power is negligible, and the standard flows for verification and test do not require change. In fact, major required components have already been integrated into several chips in production. We also use formal methods to evaluate combinational locking and computational attacks. A comprehensive protocol analysis concludes that EPIC is surprisingly resistant to various piracy attempts.