Avalanche Characteristics of Substitution-Permutation Encryption Networks
IEEE Transactions on Computers
Physical unclonable functions for device authentication and secret key generation
Proceedings of the 44th annual Design Automation Conference
Active hardware metering for intellectual property protection and security
SS'07 Proceedings of 16th USENIX Security Symposium on USENIX Security Symposium
EPIC: ending piracy of integrated circuits
Proceedings of the conference on Design, automation and test in Europe
HARPOON: an obfuscation-based SoC design methodology for hardware protection
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Secure and Robust Error Correction for Physical Unclonable Functions
IEEE Design & Test
Preventing IC Piracy Using Reconfigurable Logic Barriers
IEEE Design & Test
HOPE: an efficient parallel fault simulator for synchronous sequential circuits
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Is split manufacturing secure?
Proceedings of the Conference on Design, Automation and Test in Europe
Security analysis of integrated circuit camouflaging
Proceedings of the 2013 ACM SIGSAC conference on Computer & communications security
Hardware security: threat models and metrics
Proceedings of the International Conference on Computer-Aided Design
Proceedings of the 2014 on International symposium on physical design
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The globalization of Integrated Circuit (IC) design flow is making it easy for rogue elements in the supply chain to pirate ICs, overbuild ICs, and insert hardware trojans; the IC industry is losing approximately $4 billion annually [1], [2]. One way to protect the ICs from these attacks is to encrypt the design by inserting additional gates such that correct outputs are produced only when specific inputs are applied to these gates. The state-of-the-art logic encryption technique inserts gates randomly into the design [3] and does not necessarily ensure that wrong keys corrupt the outputs. Our technique ensures that wrong keys corrupt the outputs. We relate logic encryption to fault propagation analysis in IC testing and develop a fault analysis based logic encryption technique. This technique achieves 50% Hamming distance between the correct and wrong outputs (ideal case) when a wrong key is applied. Furthermore, this 50% Hamming distance target is achieved by using a smaller number of additional gates when compared to random logic encryption.