Implementation and testing of high-speed CMOS true random number generators based on chaotic systems

Authors:
Fabio Pareschi;Gianluca Setti;Riccardo Rovatti
Affiliations:
ENDIF, University of Ferrara, Ferrara, Italy and ARCES, University of Bologna, Bologna, Italy;ENDIF, University of Ferrara, Ferrara, Italy and ARCES, University of Bologna, Bologna, Italy;DEIS, University of Bologna, Bologna, Italy and ARCES, University of Bologna, Bologna, Italy
Venue:
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Year:
2010

Citing 18
Cited 0

A simple unpredictable pseudo random number generator

SIAM Journal on Computing
Independent unbiased coin flips from a correlated biased source:80a finite state Markov chain

Combinatorica
Elements of information theory

Elements of information theory
Handbook of Applied Cryptography

Handbook of Applied Cryptography
The Design of Rijndael

The Design of Rijndael
Supplemental Cryptographic Hardware for Smart Cards

IEEE Micro
Differential Power Analysis

CRYPTO '99 Proceedings of the 19th Annual International Cryptology Conference on Advances in Cryptology
On the Security of Random Sources

PKC '99 Proceedings of the Second International Workshop on Practice and Theory in Public Key Cryptography
A High-Speed Oscillator-Based Truly Random Number Source for Cryptographic Applications on a Smart Card IC

IEEE Transactions on Computers
Estimating Entropy Rates with Bayesian Confidence Intervals

Neural Computation
A Provably Secure True Random Number Generator with Built-In Tolerance to Active Attacks

IEEE Transactions on Computers
TestU01: A C library for empirical testing of random number generators

ACM Transactions on Mathematical Software (TOMS)
EPIC: ending piracy of integrated circuits

Proceedings of the conference on Design, automation and test in Europe
Fast Digital TRNG Based on Metastable Ring Oscillator

CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
A 3-GHz serial ATA spread-spectrum clock generator employing a chaotic PAM modulation

IEEE Transactions on Circuits and Systems Part I: Regular Papers
A robust random number generator based on a differential current-mode chaos

IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Embeddable ADC-based true random number generator for cryptographic applications exploiting nonlinear signal processing and chaos

IEEE Transactions on Signal Processing
Estimating entropy on m bins given fewer than m samples

IEEE Transactions on Information Theory

Quantified Score

Hi-index	0.00

Visualization

Abstract

We present the design and the validation by means of suitably improved randomness tests of two different implementations of high-performance true-random number generators which use a discrete-time chaotic circuit as their entropy source. The proposed system has been developed from a standard pipeline Analog-to-Digital converter (ADC) design, modified to operate as a set of piecewise-linear chaotic maps. The evolution of each map is observed and quantized to obtain a random bit stream. With this approach it is possible to obtain, on current CMOS technology, a data rate in the order of tens of megabit per second. Furthermore, we can also prove that the design is tamper resistant in the sense that a power analysis cannot leak information regarding the generated bits. This makes the proposed circuit perfectly suitable for embedding in cryptographic systems like smarts cards, even more so if one consider that it could be easily obtained by recoofiguring an existing pipeline ADC. The two prototypes have been designed in a 0.35-µm and 0.18-µm CMOS technology, and have a throughput of, respectively, 40 Mbitls and 100 Mbitls. A comparison between measured results and other high-end commercial solutions shows a comparable quality with a operating speed that is one order of magnitude faster.