Handbook of Applied Cryptography
Handbook of Applied Cryptography
Smart Card Handbook
The Art of Computer Programming, 2nd Ed. (Addison-Wesley Series in Computer Science and Information
The Art of Computer Programming, 2nd Ed. (Addison-Wesley Series in Computer Science and Information
IEEE Micro
A Design of Reliable True Random Number Generator for Cryptographic Applications
CHES '99 Proceedings of the First International Workshop on Cryptographic Hardware and Embedded Systems
CMOS Circuit Design, Layout, and Simulation, Second Edition
CMOS Circuit Design, Layout, and Simulation, Second Edition
A Design for a Physical RNG with Robust Entropy Estimators
CHES '08 Proceeding sof the 10th international workshop on Cryptographic Hardware and Embedded Systems
CAIP'07 Proceedings of the 12th international conference on Computer analysis of images and patterns
WISA'10 Proceedings of the 11th international conference on Information security applications
Jitter amplifier for oscillator-based true random number generator
Proceedings of the 16th Asia and South Pacific Design Automation Conference
Implementation and testing of high-speed CMOS true random number generators based on chaotic systems
IEEE Transactions on Circuits and Systems Part I: Regular Papers - Special section on 2009 IEEE system-on-chip conference
Ultra-Low Power Truly Random Number Generator for RFID Tag
Wireless Personal Communications: An International Journal
Towards a secure and practical multifunctional smart card
CARDIS'06 Proceedings of the 7th IFIP WG 8.8/11.2 international conference on Smart Card Research and Advanced Applications
ISCIS'05 Proceedings of the 20th international conference on Computer and Information Sciences
Design of testable random bit generators
CHES'05 Proceedings of the 7th international conference on Cryptographic hardware and embedded systems
A holistic approach examining RFID design for security and privacy
The Journal of Supercomputing
A novel design method for discrete time chaos based true random number generators
Integration, the VLSI Journal
| Hi-index | 14.98 |
The design of a high-speed IC random number source macro-cell, suitable to be integrated in a Smart Card microcontroller, is presented. The oscillator sampling technique is exploited and a jittered oscillator which features an amplified thermal noise source has been designed in order to increase the output throughput and the statistical quality of the generated bit sequences. The oscillator feedback loop acts as an offset compensation for the noise amplifier, thus solving one of the major issues in this kind of circuit. A numerical model for the proposed system has been developed which allows us to carry out an analytical expression for the transition probability between successive bits in the output stream. A prototype chip has been fabricated in a standard digital 0.18\mu mn-well CMOS process which features a 10Mbps throughput and fulfills the NIST FIPS and correlation-based tests for randomness. The macro-cell area, excluding pads, is 0.0016mm^{2} (184\mu m \times 86\mu m) and a 2.3mW power consumption has been measured.