Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Architecture and CAD for Deep-Submicron FPGAs
Architecture and CAD for Deep-Submicron FPGAs
The stratixπ routing and logic architecture
FPGA '03 Proceedings of the 2003 ACM/SIGDA eleventh international symposium on Field programmable gate arrays
Evaluation of low-leakage design techniques for field programmable gate arrays
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
A detailed power model for field-programmable gate arrays
ACM Transactions on Design Automation of Electronic Systems (TODAES)
An Overview of Low-Power Techniques for Field-Programmable Gate Arrays
AHS '08 Proceedings of the 2008 NASA/ESA Conference on Adaptive Hardware and Systems
Architectural enhancements in Stratix-III™ and Stratix-IV™
Proceedings of the ACM/SIGDA international symposium on Field programmable gate arrays
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research
FCCM '10 Proceedings of the 2010 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines
Technology mapping and clustering for FPGA architectures with dual supply voltages
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
Improvements to Technology Mapping for LUT-Based FPGAs
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In this paper, we present a novel routing architecture for FPGAs with dual-VT LUT and switch box architectures. The use of reverse back bias (RBB) is one strategy for mitigating leakage power, a critical issue as process technologies shrink relentlessly towards sub-nano proportions. FPGAs with the ability to adjust fabric VT at configuration time offer leakage power reduction without sacrificing circuit speed. Most of the related works today investigate dual-VT optimizations at the logic cluster level; Altera's Stratix-III/IV line of FPGAs already demonstrate the feasibility of a similar architecture. In this work, we present a further advancement to the dual-VT architecture - the switch box, and a routing architecture that demonstrates the effectiveness of this true dual-VT fabric architecture. Our switch box advancement alone yields an average of 17.44% in leakage power savings, and with the full EDA flow an average 29.65% in total power savings is observed.