Combining optimizations in automated low power design
Proceedings of the Conference on Design, Automation and Test in Europe
New configuration memory cells for FPGA in nano-scaled CMOS technology
Microelectronics Journal
Selective instruction set muting for energy-aware adaptive processors
Proceedings of the International Conference on Computer-Aided Design
Power-aware FPGA technology mapping for programmable-VT architectures (abstract only)
Proceedings of the ACM/SIGDA international symposium on Field Programmable Gate Arrays
A routing architecture for FPGAs with Dual-VT switch box and logic clusters
ARC'12 Proceedings of the 8th international conference on Reconfigurable Computing: architectures, tools and applications
Low-leakage soft error tolerant port-less configuration memory cells for FPGAs
Integration, the VLSI Journal
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This paper provides an overview of low-power techniques for field-programmable gate arrays (FPGAs). It covers system-level design techniques and device-level design techniques that have targeted current commercial devices. It also describes current research on circuit-level and architecture-level design techniques. Recent studies on power modelling and on low-power computer-aided design (CAD) are also reported. Finally, it proposes future work that would enable the use of FPGA technology in applications where power and energy consumption is critical, such as mobile devices.