Dynamic Vdd switching technique and mapping optimization in dynamically reconfigurable processor for efficient energy reduction

Authors:
Tatsuya Yamamoto;Kazuei Hironaka;Yuki Hayakawa;Masayuki Kimura;Hideharu Amano;Kimiyoshi Usami
Affiliations:
Graduate School of Engineering, Shibaura Institute of Technology, Tokyo, Japan;Graduate School of Fundamental Science and Technology, Keio University, Kanagawa, Japan;Graduate School of Engineering, Shibaura Institute of Technology, Tokyo, Japan;Graduate School of Fundamental Science and Technology, Keio University, Kanagawa, Japan;Graduate School of Fundamental Science and Technology, Keio University, Kanagawa, Japan;Graduate School of Engineering, Shibaura Institute of Technology, Tokyo, Japan
Venue:
ARC'11 Proceedings of the 7th international conference on Reconfigurable computing: architectures, tools and applications
Year:
2011

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Abstract

This paper describes a dynamic VDD switching technique to reduce energy dissipation of Dynamically Reconfigurable Processors. Either high or low supply is dynamically selected at each PE at the context-by-context basis. We designed a part of a PE array and applied this technique. A test chip fabricated in 65nm technology operated successfully. Detailed simulations revealed that energy reduction is hindered by energy overhead due to supply switching when we use even lower VDD. We propose a mapping optimization algorithm "PFCM" to minimize the overhead. PFCM reduced energy overhead by 90.8% and thereby the dynamic VDD switching technique reduced energy dissipation by up to 12.5% when running sepia filter, alpha blender and Laplacian filter programs.