Clustered voltage scaling technique for low-power design
ISLPED '95 Proceedings of the 1995 international symposium on Low power design
Layout techniques supporting the use of dual supply voltages for cell-based designs
Proceedings of the 36th annual ACM/IEEE Design Automation Conference
Optimization of VDD and VTH for low-power and high speed applications
ASP-DAC '00 Proceedings of the 2000 Asia and South Pacific Design Automation Conference
Analysis and design of low-energy flip-flops
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics
FPGA '04 Proceedings of the 2004 ACM/SIGDA 12th international symposium on Field programmable gate arrays
Level conversion for dual-supply systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment
Proceedings of the 41st annual Design Automation Conference
A new algorithm for improved VDD assignment in low power dual VDD systems
Proceedings of the 2004 international symposium on Low power electronics and design
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Multi-story power delivery for supply noise reduction and low voltage operation
ISLPED '05 Proceedings of the 2005 international symposium on Low power electronics and design
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
Proceedings of the 2006 international symposium on Physical design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
| Hi-index | 0.00 |
Dual-supply voltage design using a clustered voltage scaling (CVS) scheme is an effective approach to reduce chip power. The optimal CVS design relies on a level converter (LC) implemented in a flip-flop to minimize energy, delay, and area penalties due to level conversion. Novel flip-flops presented in this paper incorporate a half-latch LC and a precharged LC. These flip-flops are optimized in the energy-delay design space to achieve over 30% reduction of energy-delay product and about 10% savings of total power in a CVS design as compared to the conventional flip-flop. These benefits are accompanied by 24% robustness improvement and 18% layout area reduction.