Logical effort: designing fast CMOS circuits
Logical effort: designing fast CMOS circuits
ISLPED '01 Proceedings of the 2001 international symposium on Low power electronics and design
Digital System Clocking: High-Performance and Low-Power Aspects
Digital System Clocking: High-Performance and Low-Power Aspects
Level conversion for dual-supply systems
Proceedings of the 2003 international symposium on Low power electronics and design
Clocking and clocked storage elements in a multi-gigahertz environment
IBM Journal of Research and Development
High performance level conversion for dual VDD design
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Dual-edge triggered storage elements and clocking strategy for low-power systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Level Converting Flip-Flops for High-Speed and Low-Power Applications
IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences
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Level converting flip-flops (LCFFs) are crucial components for multisupply systems as interfaces between different voltage islands. The proposed energy-efficient LCFFs reduce the power consumption of clock networks with dual-edge triggering, support sleep mode of power management mechanisms with data retention, and have symmetry in setup times and insensitivity to output parasitics. With all these features, the proposed LCFFs have 19% and 38% lower power-delay product than the conventional LCFF, as demonstrated by postlayout simulation results.