Can recursive bisection alone produce routable placements?
Proceedings of the 37th Annual Design Automation Conference
Duet: an accurate leakage estimation and optimization tool for dual-Vt circuits
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
IEEE Transactions on Very Large Scale Integration (VLSI) Systems - Special section on low power
Statistical Timing Analysis Considering Spatial Correlations using a Single Pert-Like Traversal
Proceedings of the 2003 IEEE/ACM international conference on Computer-aided design
Active mode leakage reduction using fine-grained forward body biasing strategy
Proceedings of the 2004 international symposium on Low power electronics and design
ISQED '05 Proceedings of the 6th International Symposium on Quality of Electronic Design
An efficient algorithm for statistical minimization of total power under timing yield constraints
Proceedings of the 42nd annual Design Automation Conference
Robust gate sizing by geometric programming
Proceedings of the 42nd annual Design Automation Conference
Extraction of statistical timing profiles using test data
Proceedings of the 44th annual Design Automation Conference
Unified adaptivity optimization of clock and logic signals
Proceedings of the 2007 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Variation-aware gate sizing and clustering for post-silicon optimized circuits
Proceedings of the 13th international symposium on Low power electronics and design
System-level mitigation of WID leakage power variability using body-bias islands
CODES+ISSS '08 Proceedings of the 6th IEEE/ACM/IFIP international conference on Hardware/Software codesign and system synthesis
Evaluation of voltage interpolation to address process variations
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Proceedings of the 2009 International Conference on Computer-Aided Design
FPGA design for timing yield under process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
Proceedings of the 47th Design Automation Conference
Design time body bias selection for parametric yield improvement
Proceedings of the 2010 Asia and South Pacific Design Automation Conference
Automating design of voltage interpolation to address process variations
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
CODES+ISSS '11 Proceedings of the seventh IEEE/ACM/IFIP international conference on Hardware/software codesign and system synthesis
A lower bound computation method for evaluation of statistical design techniques
Proceedings of the International Conference on Computer-Aided Design
Structured analog circuit design and MOS transistor decomposition for high accuracy applications
Proceedings of the International Conference on Computer-Aided Design
Low-power resource binding by postsilicon customization
ACM Transactions on Design Automation of Electronic Systems (TODAES)
System-level leakage variability mitigation for MPSoC platforms using body-bias islands
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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Adaptive body biasing (ABB) is a powerful technique that allows post-silicon tuning of individual manufactured dies such that each die optimally meets the delay and power constraints. Assigning individual bias control to each gate leads to severe overhead, rendering the method impractical. However, assigning a single bias control to all gates in the circuit prevents the method from compensating for intra-die variation and greatly reduces its effectiveness. In this paper, we propose a new variability-aware method that clusters gates at design time into a handful of carefully chosen independent body bias groups, which are then individually tuned post-silicon for each die. We show that this allows us to obtain near-optimal performance and power characteristics with minimal overhead. For each gate, we generate the probability distribution of its post-silicon ideal body bias voltage using an efficient sampling method. We then use these distributions and their correlations to drive a statistically-aware clustering technique. We study the physical design constraints and show how the area and wirelength overhead can be significantly limited using the proposed method. Compared to a fixed design time based dual threshold voltage assignment method, we improve leakage power by 38-71% while simultaneously reducing the standard deviation of delay by 2-9X.