Potential slack: an effective metric of combinational circuit performance
Proceedings of the 2000 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2002 IEEE/ACM international conference on Computer-aided design
Proceedings of the 2003 international symposium on Low power electronics and design
Re-synthesis for delay variation tolerance
Proceedings of the 41st annual Design Automation Conference
Active mode leakage reduction using fine-grained forward body biasing strategy
Proceedings of the 2004 international symposium on Low power electronics and design
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
VLSID '05 Proceedings of the 18th International Conference on VLSI Design held jointly with 4th International Conference on Embedded Systems Design
A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents
Proceedings of the 42nd annual Design Automation Conference
Statistical static timing analysis: how simple can we get?
Proceedings of the 42nd annual Design Automation Conference
A statistical framework for post-silicon tuning through body bias clustering
Proceedings of the 2006 IEEE/ACM international conference on Computer-aided design
Variability-driven module selection with joint design time optimization and post-silicon tuning
Proceedings of the 2008 Asia and South Pacific Design Automation Conference
Parameterized timing analysis with general delay models and arbitrary variation sources
Proceedings of the 45th annual Design Automation Conference
Variation-aware gate sizing and clustering for post-silicon optimized circuits
Proceedings of the 13th international symposium on Low power electronics and design
Efficient block-based parameterized timing analysis covering all potentially critical paths
Proceedings of the 2008 IEEE/ACM International Conference on Computer-Aided Design
Design-Time Optimization of Post-Silicon Tuned Circuits Using Adaptive Body Bias
IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems
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In recent years, fabrication technology of CMOS has scaled to nanometer dimensions. As scaling progresses, several new challenges follow. Among them, the most noticeable two are process variations and leakage current of the circuit. To tackle the problems of process variations and leakage current, an effective way is to use a body-biasing technique. In substance, using the RBB technique can minimize leakage current but increase the delay of a gate. Contrary to RBB, the FBB technique decreases the delay but increases leakage current of a gate. In the previous work, a single body-biasing is applied to the whole circuit. In a slow circuit, since the FBB is applied to the whole circuit, the leakage current of all gates in the circuit increases dramatically. On the other hand, in a fast circuit, RBB is applied to decrease the leakage current. However, without violating the timing specification, the value of body-biasing is restricted by the critical paths, and the saving of leakage current is limited. In this article, we propose a design flow to partition the circuit into subcircuits so that each subcircuit can be applied its individual RBB or FBB. Experiments show that our method is able to save leakage current from 42% to 47% as compared to designs not using a body-biasing technique. Under process variations, our method can save 42% to 49% leakage on fast circuits and 20% to 35% on slow circuits.