Impact of Gate-Length Biasing on Threshold-Voltage Selection
ISQED '06 Proceedings of the 7th International Symposium on Quality Electronic Design
Dynamic power management under uncertain information
Proceedings of the conference on Design, automation and test in Europe
Leakage reduction, delay compensation using partition-based tunable body-biasing techniques
ACM Transactions on Design Automation of Electronic Systems (TODAES)
Uncertainty-aware dynamic power management in partially observable domains
IEEE Transactions on Very Large Scale Integration (VLSI) Systems
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One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage reduction techniques on delay/leakage uncertainty is examined through Monte-Carlo analysis. The techniques investigated in this paper include increasing gate length, stack forcing, body biasing, and V_dd/V_th optimization. The impact of technology scaling and temperature sensitivity on the uncertainty reduction are also evaluated. We investigate the uncertainty-power-delay trade-off and suggest techniques for designs targeting different requirements.